The invention relates to a semiconductor packaging and in particular to a method for mounting passive components on a wafer.
Typically, the fabrication of microelectronic device comprises three main steps. First, a semiconductor substrate is provided by epitaxy technology. Second, integrated circuits are formed on the substrate, which comprises semiconductor devices and metal interconnects for electrical connection therebetween. Third, packaging is performed on the substrate to protect the integrated circuits on the substrate and provide a signal transmission interface for external circuits. In order to fabricate semiconductor devices with high integration for thin profile and lightweight electronic products, a variety of packaging technologies have been developed, such as ball grid array (BGA), wafer scale package (CSP), flip wafer, and multi-wafer module (MCM).
In semiconductor packaging, a wafer having integrated circuits thereon is diced into wafers or dies. Next, the wafer or die having bonding pads thereon is arranged on a carrier, such as a leadframe or a package substrate, by wire bonding or flip-wafer bonding. Generally, the passive component is mounted on the package substrate by surface mount technology (SMT) after packaging. The passive component is electrically connected to the integrated circuits on the wafer through the circuits on the package substrate.
Since the passive component mounted on the substrate is electrically connected to the integrated circuits on the wafer through the circuits on the package substrate, a long signal transmission path is created therebetween. As a result, the performance of semiconductor devices is reduced due to RC delay. A reduced signal transmission path between the passive component and the wafer is thus desirable to attain a semiconductor device with high performance and high integration.